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ISL6225
Data Sheet September 2003 FN9049.4
Dual Mobile-Friendly PWM Controller with DDR Memory Option
The ISL6225 dual PWM controller delivers high efficiency and tight regulation from two voltage regulating synchronous buck DC/DC converters. The ISL6225 PWM power supply controller was designed especially for DDR DRAM, SDRAM, and graphic chipset applications in high performance desknote PCs, notebook PCs, sub-notebook PCs, and PDAs. Automatic mode selection of constant-frequency synchronous rectification at heavy load, and hysteretic diode-emulation at light load, assure high efficiency over a wide range of conditions. The hysteretic mode of operation can be disabled separately on each PWM converter if constant-frequency continuous-conduction operation is desired for all load levels. Efficiency is further enhanced by using the lower MOSFET RDS(ON) as the current sense element. Voltage-feed-forward ramp modulation, average current mode control, and internal feedback compensation provide fast response to input voltage and output load transients. Input current ripple is minimized by channel to channel PWM phase shift of 0, 90, or 180 determined by input voltage and status of the DDR pin. The ISL6225 can control two independent output voltages adjustable from 0.9V to 5.5V or, by activating the DDR pin, transform into a complete DDR memory power supply solution. In DDR mode, CH2 output voltage VTT tracks CH1 output voltage VDDQ. CH2 output can both source and sink current, an essential power supply feature for DDR memory systems. The reference voltage VREF required by DDR memory is generated as well. In dual power supply applications the ISL6225 monitors the output voltage of both CH1 and CH2. An independent PGOOD (power good) signal is asserted for each channel after the soft-start sequence has completed, and the output voltage is within 10% of the set point. In DDR mode CH1 generates the only PGOOD signal. Built-in over-voltage protection prevents the output from going above 115% of the set point by holding the lower MOSFET on and the upper MOSFET off. When the output voltage decays below the over-voltage threshold, normal operation automatically resumes. Once the soft-start sequence has completed, under-voltage protection may latch the ISL6225 off if either output drops below 75% of its set point value. Adjustable over-current protection (OCP) monitors the voltage drop across the RDS(ON) of the lower MOSFET. If more precise current-sensing is required, an external current sense resistor may be used.
Features
* Provides regulated output voltage in the range of 0.9V-5.5V - High efficiency over wide load range - Synchronous buck converter with hysteretic operation at light load - Inhibit Hysteretic mode on one, or both channels * Complete DDR memory power solution - VTT tracks VDDQ/2 - VDDQ/2 buffered reference output * No current-sense resistor required - Uses MOSFET RDS(ON) - Optional current-sense resistor for precision Over-Current * Under-voltage lock-out on VCC pin * Dual input voltage mode operation - Operates directly from battery 5V to 24V input - Operates from 3.3V or 5V system rail - VCC from 5V only * Excellent dynamic response - Combined voltage feed-forward and average current mode control * Power-good signal for each channel * 300kHz switching frequency - 180 channel to channel phase operation for reduced input ripple when not in DDR mode - 0 channel to channel phase operation in DDR mode for reduced channel interference - 90 channel to channel phase operation for reduced input ripple in DDR mode when VIN is at GND.
Applications
* Mobile PCs * PDAs * Hand-held portable instruments
Pinout
ISL6225 SSOP-28 TOP VIEW
GND 1 LGATE1 2 PGND1 3 PHASE1 4 UGATE1 5 BOOT1 6 ISEN1 7 EN1 8 VOUT1 9 28 VCC 27 LGATE2 26 PGND2 25 PHASE2 24 UGATE2 23 BOOT2 22 ISEN2 21 EN2 20 VOUT2 19 VSEN2 18 OCSET2 17 SOFT2 16 PG2/REF 15 PG1
Ordering Information
PART NUMBER ISL6225CA ISL6225CA-T TEMP. (oC) -10 to 85 -10 to 85 PACKAGE 28 Ld SSOP 28 Ld SSOP Tape and Reel PKG. NO. M28.15 M28.15
VSEN1 10 OCSET1 11 SOFT1 12 DDR 13 VIN 14
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6225
Absolute Maximum Ratings
Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 6.5V Input Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27.0V PHASE, UGATE Voltage. . . . . . . . . . . . . . . . GND-5V (Note1) to 33V BOOT, ISEN Voltage. . . . . . . . . . . . . . . . . . . . . GND-0.3V to +33.0V BOOT with respect to PHASE. . . . . . . . . . . . . . . . . . . . . . . . . + 6.5V All Other Pins. . . . . . . . . . . . . . . . . . . . . . . .GND -0.3V to VCC + 0.3V ESD Classification. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 2)
JA (oC/W)
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SSOP - Lead Tips Only)
Recommended Operating Conditions
Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V 5% Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V to +24.0V Ambient Temperature Range. . . . . . . . . . . . . . . . . . . -10oC to 85oC Junction Temperature Range . . . . . . . . . . . . . . . . . -10oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. 200ns transient. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER VCC SUPPLY Bias Current Shut-down Current VCC UVLO Rising VCC Threshold Falling VCC Threshold VIN Input Voltage Pin Current (Sink) Input Voltage Pin Current (Source) Shut-down Current OSCILLATOR PWM1 Oscillator Frequency Ramp Amplitude, pk-pk Ramp Amplitude, pk-pk Ramp Offset Ramp/VIN Gain Ramp/VIN Gain REFERENCE AND SOFT START Internal Reference Voltage Reference Voltage Accuracy Soft-Start Current During Start-up Soft-Start Complete Threshold PWM CONVERTERS Load Regulation VSEN pin bias current VOUT pin input impedance
Recommended Operating Conditions, Unless Otherwise Noted. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ICC ICCSN VCCU VCCD IVIN IVINO IVINS FC VR1 VR2 VROFF GRB1 GRB2 VREF ISOFT VST
LGATEx, UGATEx Open, VSENx forced above regulation point, DDR=0, VIN>5V
-
2.2 -
3.2 30
mA A
4.3 4.1
4.65 4.35
4.75 4.45
V V A A A
10 -
-15 -
30 -30 1
255 VIN = 16V, by design VIN = 5V, by design By design VIN 3V, by design 1 VIN 3V, by design -
300 2 1.25 0.5 125 250
345 -
kHz V V V mV/V mV/V
-1.0 By design
0.9 -5 1.5
+1.0 -
V % A V
0.0mA < IVOUT1 < 5.0A; 5.0V < VBATT < 24.0V IVSEN IVOUT By design VOUT = 5V
-2.0 50 40
80 55
+2.0 120 65
% nA k
2
ISL6225
Electrical Specifications
PARAMETER Under-Voltage Shut-Down Level Over-Voltage Shut-Down GATE DRIVERS Upper Drive Pull-Up Resistance Upper Drive Pull-Down Resistance Lower Drive Pull-Up Resistance Lower Drive Pull-Down Resistance POWER GOOD AND CONTROL FUNCTIONS Power Good Lower Threshold Power Good Higher Threshold PGOODx Leakage Current PGOODx Voltage Low EN - Low (Off) EN - High (On) CCM Enforced (Hysteretic Operation Inhibited) Automatic CCM/Hysteretic Operation Enabled DDR - Low (Off) DDR - High (On) DDR REF Output Voltage DDR REF Output Current VDDREF IDDREF DDR=1, IREF=0...10mA DDR=1. Guaranteed by design. VOUTX pulled low VOUTX connected to the output VPGVPG+ IPGLKG VPGOOD Fraction of the set point; ~3s noise filter Fraction of the set point; ~3s noise filter. Guaranteed by design. VPULLUP = 5.5V IPGOOD = -4mA -13 12 2.5 0.9 2.5 0.99* VOC2 0.5 VOC2 10 -7 16 1 0.85 0.8 0.1 0.8 1.01* VOC2 16 % % A V V V V V V V V mA R2UGPUP R2UGPDN R2LGPUP R2LGPDN VCC=4.5V VCC=4.5V VCC=4.5V VCC=4.5V 8 3.2 8 1.8 15 5 15 3 Recommended Operating Conditions, Unless Otherwise Noted. (Continued) SYMBOL VUVL VOVP1 TEST CONDITIONS Fraction of the set point; ~2s noise filter Fraction of the set point; ~2s noise filter MIN 70 110 TYP MAX 85 130 UNITS % %
3
ISL6225 Functional Pin Description
GND (Pin 1)
Signal ground for the IC.
SOFT1, SOFT2 (Pin 12, 17)
These pins provide soft-start function for their respective controllers. When the chip is enabled, the regulated 5A pull-up current source charges the capacitor connected from the pin to ground. The output voltage of the converter follows the ramping voltage on the SOFT pin.
LGATE1, LGATE2 (Pin 2, 27)
These are outputs of the lower MOSFET drivers.
PGND1, PGND2 (Pin 3, 26)
These pins provide the return connection for lower gate drivers. These pins are connected to sources of the lower MOSFETs of their respective converters.
DDR (Pin 13)
This pin, when high, transforms dual channel chip into complete DDR memory solution. The OCSET2 pin becomes an input to provide the required tracking function. The channel synchronization is changed from out-of-phase to inphase. The PG2/REF pin becomes the output of the VDDQ/ 2 buffered voltage that is used as a reference voltage by the second channel.
PHASE1, PHASE2 (Pin 4, 25)
The PHASE1 and PHASE2 points are the junction points of the upper MOSFET sources, output filter inductors, and lower MOSFET drains. Connect these pins to the respective converter's upper MOSFET source.
VIN (Pin 14)
Provides battery voltage to the oscillator for feed-forward rejection of the input voltage variation. When connected to ground via 100k resistor while the DDR pin is high, this pin commands the out-of-phase 90o channels synchronization for reduces inter-channel interference.
UGATE1, UGATE2 (Pin 5, 24)
These pins provide the gate drive for the upper MOSFETs.
BOOT1, BOOT2 (Pin 6, 23)
These pins power the upper MOSFET drivers of the PWM converter. Connect this pin to the junction of the bootstrap capacitor with the cathode of the bootstrap diode. Anode of the bootstrap diode is connected to the VCC pin.
PG1 (Pin 15)
PGOOD1 is an open drain output used to indicate the status of the output voltage. This pin is pulled low when the first channel output is not within 10% of the set value.
ISEN1, ISEN2 (Pin 7, 22)
These pins are used to monitor the voltage drop across the lower MOSFET for current feedback and Over-Current protection. For precise current detection these inputs can be connected to the optional current sense resistors placed in series with the source of the lower MOSFETs.
PG2/REF (Pin 16)
This pin has a double function depending on the mode the chip is operating. When the chip is used as a dual channel PWM controller (DDR=0), the pin provides a PGOOD2 function for the second channel. The pin is pulled low when the second channel output is not within 10% of the set value. In DDR mode (DDR=1), this pin serves as an output of the buffer amplifier that provides VDDQ/2 reference voltage applied to the OCSET2 pin.
EN1, EN2 (Pin 8, 21)
These pins enable operation of the respective converter when high. When both pins are low, the chip is disabled and only low leakage current <1A is taken from VCC and VIN. These pins are to be connected together and switched at the same time.
OCSET2 (Pin 18)
In a dual channel application (DDR=0), a resistor from this pin to ground sets the over current threshold for the second controller. In the DDR application (DDR=1), this pin sets the output voltage of the buffer amplifier and the second controller and should be connected to the center point of a divider from the VDDQ output.
VOUT1, VOUT2 (Pin 9, 20)
These pins when connected to the converters' respective outputs provide the output voltage inside the chip to reduce output voltage excursion during HYS/PWM transition. When connected to ground, these pins command forced converters operate in continuous conduction mode at all load levels.
VSEN1, VSEN2 (Pin 10, 19)
These pins are connected to the resistive dividers that set the desired output voltage. The PGOOD, UVP, and OVP circuits use this signal to report output voltage status.
VCC (Pin 28)
This pin powers the controller.
OCSET1 (Pin 11)
A resistor from this pin to ground sets the over current threshold for the first controller.
4
ISL6225 Generic Application Circuits
ENABLE
OCSET1
Q1 L1 VOUT1 + +1.80V
PWM1 Q2 +VIN +3.3V TO +24V EN1 EN2 VCC DDR +5V OCSET2 PWM2 C1
Q3 L2 VOUT2 + +1.20V
Q4
C2
FIGURE 1. ISL6225 APPLICATION CIRCUIT FOR TWO CHANNEL POWER SUPPLY
ENABLE
OCSET1
Q1 L1 VDDQ PWM1 Q2 C1 + +2.50V
+VIN +3.3V TO +24V
EN1 EN2 VCC DDR +5V PG2/VREF PWM2 OCSET2 Q4 C2 + Q3 L2 VTT +1.25V
VREF +1.25V
FIGURE 2. ISL6225 APPLICATION CIRCUIT FOR COMPLETE DDR MEMORY POWER SUPPLY
5
Block Diagram
BOOT1 UGATE1 PHASE1 PGND1 LGATE1 VCC DDR=1 DDR=0 SOFT1 PG1 EN1 VOUT1 VCC GND VOUT2 EN2 REF/PG2 SOFT2 BOOT2 UGATE2 PHASE2 PGND2 LGATE2 VCC POR
ADAPTIVE DEAD-TIME DIODE EMULATION V/I SAMPLE TIMING PWM/HYS TRANSITION
ADAPTIVE DEAD-TIME DIODE EMULATION V/I SAMPLE TIMING PWM/HYS TRANSITION
6
+
MODE CHANGE COMP 1 ENABLE
+ SAME STATE FOR 8 CLOCK CYCLES REQUIRED TO CHANGE PWM OR HYS MODE BIAS SUPPLIES REFERENCE FAULT LATCH SAME STATE FOR 8 CLOCK CYCLES REQUIRED TO CHANGE PWM OR HYS MODE
MODE CHANGE COMP 2
-
HYSTERETIC COMPARATOR 1
+
- HYSTERETIC COMPARATOR 2 +
VHYS=15mV SOFT START 15.2pF OV UV PGOOD VOLTS/SEC CLAMP 1.3pF OC1 DDR OC2 DDR MODE CONTROL OV UV PGOOD
VHYS=15mV
1M 500k VSEN1 300k
15.2pF VOLTS/SEC CLAMP
1M
ISL6225
500k 1.3pF 300k VSEN2
+
+ 0.9V REFERENCE ERROR AMP 1
+
PWM1
PWM2
+
ERROR AMP 2
+
DDR=0 DDR=1
DUTY CYCLE RAMP GENERATOR PWM CHANNEL PHASE CONTROL
0.9V REFERENCE
+
DDR EN1 EN2
ISEN1 100
VIN 0 24.0V 4.2 < VIN < 24.0V VIN to GND
CH1CH2 1 80 0 90
CURRENT SAMPLE 100 ISEN2
0
1 1
1 1
CURRENT SAMPLE
+
CURRENT SAMPLE
+
CURRENT SAMPLE
1
OCSET1 + 0.9V REFERENCE 0.9V REFERENCE +
DDR=0
OCSET2 DDR=1
+
1/3 OCSET1 1/32 ISEN1
OC1
OC2
+ + DDR VREF BUFFER AMP
SAME STATE FOR 8 CLOCK CYCLES REQUIRED TO LATCH OVER-CURRENT FAULT
VIN
DDR
VCC
SAME STATE FOR 8 CLOCK CYCLES REQUIRED TO LATCH OVER-CURRENT FAULT
1/32 ISEN2
1/3 OCSET2
+ DDR VTT REFERENCE
ISL6225 Description
Operation
The ISL6225 is a dual channel PWM controller intended for use in power supplies for graphic chipset, SDRAM, DDR DRAM or other low voltage power applications in modern notebook and sub-notebook PCs. The IC integrates two control circuits for two synchronous buck converters. The output voltage of each controller can be set in the range of 0.9V to 5.5V by an external resistive divider. Out-of-phase operation with 180 degree phase shift reduces input current ripple. The synchronous buck converters can operate from either an unregulated DC source such as a notebook battery with a voltage ranging from 5.0V to 24V, or from a regulated system rail of 3.3V or 5V. In either mode of operation the controller is biased from the +5V source. The controllers operate in the current mode with input voltage feed-forward for simplified feedback loop compensation and reduced effect of the input voltage variation. An integrated feedback loop compensation dramatically reduces the number of external components. Depending on the load level, converters can operate either in a fixed-frequency mode or in a hysteretic mode. Switchover to the hysteretic mode operation at light loads improves the converters' efficiency and prolongs battery run time. The hysteretic mode of operation can be inhibited independently for each channel if a variable frequency operation is not desired. The ISL6225 has a special means to rearrange its internal architecture into a complete DDR solution. When DDR input is set high, the second channel can provide the capability to track the output voltage of the first channel. The buffered reference voltage required by DDR memory chips is also provided. 1.5V, the power good (PGOOD), the mode control, and the fault functions are enabled, as depicted in Figure 3.
EN 1
0.9V 2
1.5V SOFT
VOUT 3 PGOOD 4 Ch1 5.0V Ch3 1.0V Ch2 2.0V Ch4 5.0V M1.00ms
FIGURE 3. START UP
This completes the soft start sequence. Further rise of pin voltage does not affect the output voltage. During the softstart, the converter always operates in continuous conduction mode independently of the load level or FCCM pin potential. The soft-start time (the time from the moment when EN becomes high to the moment when PGOOD is reported) is determined by the following equation.
1.5V x Csoft T SOFT = ------------------------------5A
The time it takes the output voltage to come into regulation can be obtained from the following equation.
T RISE = 0.6 x T SOFT
Initialization
The Power-On Reset (POR) function continually monitors the bias supply voltage on the VCC pin and initiates soft-start operation after the input supply voltage exceeds 4.5V. Should this voltage drop lower than 4.0V, the POR disables the chip.
Having such a spread between the time when the output voltage reaches the regulation point and the moment when PGOOD is reported allows for a fault-safe test mode by means of an external circuit that clamps the SOFT pin voltage on the level 0.9VOutput Voltage Program
The output voltage of either channel is set by a resistive divider from the output to ground. The center point of the divider is connected to VSEN pin as shown in Figure 4. The output voltage value is determined by the following equation.
0.9V * ( R1 + R2 ) V O = -----------------------------------------R2
Soft-Start
When soft start is initiated, the voltage on the SOFT pin starts to ramp gradually due to the 5A current sourced into the external soft-start capacitor. The output voltage starts to follow the soft-start voltage. When the SOFT pin voltage reaches a level of 0.9V, the output voltage comes into regulation while the soft-start pin voltage continues to rise. When the SOFT voltage reaches
Where 0.9V is the value of the internal reference. The VSEN pin voltage is also used by the controller for the power good function and to detect Under-Voltage and Over-Voltage conditions.
7
ISL6225
Automatic Operation Mode Control
In nominal currents the synchronous buck converter operates in continuous-conduction constant-frequency mode. This mode of operation achieves higher efficiency due to the substantially lower voltage drop across the synchronous MOSFET compared to a Shottky diode. In contrast, continuous-conduction operation with load currents lower than the inductor critical value results in lower efficiency. In this case, during a fraction of a switching cycle, the direction of the inductor current changes to the opposite, actively discharging the output filter capacitor.
VIN Q1 L1 RCS LGATE Q2 R1 C1 Cz
The voltage across the synchronous MOSFET at the moment of time just before the upper-MOSFET turns on is monitored for purposes of mode change. When the converter operates at currents higher than critical, this voltage is always negative. In currents lower than critical, the voltage is always positive. The mode control circuit uses a sign of voltage across the synchronous devices to determine if the load current is higher or lower than the critical value. To prevent chatter between operating modes, the circuit looks for eight contiguous signals of the same polarity before it makes the decision to perform a mode change. The same algorithm is true for both CCM-hysteretic and hystereticCCM transitions.
UGATE ISEN
Hysteretic Operation
When the critical inductor current is detected, the converter enters hysteretic mode. The PWM comparator and the error amplifier that provided control in the CCM mode are inhibited and the hysteretic comparator is now activated. A change is also made to the gate logic. In hysteretic mode the synchronous rectifier MOSFET is controlled in diode emulation mode, hence conduction in the second quadrant is prohibited.
VOUT VSEN OCSET ISL6225 ROC
R2
VOUT t
FIGURE 4. OUTPUT VOLTAGE PROGRAM
To maintain the output voltage in regulation, the discharged energy should be restored during the consequent cycle of operation by the cost of increased circulating current and losses associated with it. The critical value of the inductor current can be estimated by the following expression:
( V IN - V O ) * V O I HYS = -------------------------------------------------2 * F SW * L O * V IN
IIND
t
PHASE COMP 12345 678 MODE OF OPERATION PWM HYSTERETIC t t
FIGURE 5. CCM -- HYSTERETIC TRANSITION
To improve converter efficiency at loads lower than critical, the switch-over to variable frequency hysteretic operation with diode emulation is implemented into the PWM scheme. The switch-over is provided automatically by the mode control circuit that constantly monitors the inductor current and alters the way the PWM signal is generated.
VOUT
t
IIND 1 PHASE COMP 2345 678
t
t HYSTERETIC PWM t
MODE OF OPERATION
FIGURE 6. HYSTERETIC -- CCM TRANSITION
8
ISL6225
The hysteretic comparator initiates the PWM signal when the output voltage gets below the lower threshold and terminates the PWM signal when the output voltage rises above the upper threshold. A spread or hysteresis between these two thresholds determines the switching frequency and the peak value of the inductor current. The transition to constant frequency CCM mode happens when the inductor current increases above the critical value:
V hys I CCM ------------------2 * ESR
the ISEN pin sets the gain in the current feedback loop. The following expression estimates the required value of the current sense resistor depending on the maximum load current and the value of the MOSFET's RDS(ON).
R CS I R MAX DS ( ON ) = --------------------------------------------- - 100 75A
Due to implemented current feedback, the modulator has a single pole response with -1 slope at a frequency determined by the load,
F PO 1 = ------------------------------2 R C OO
Where, Vhys= 15mV, is a hysteretic comparator window, ESR is the equivalent series resistance of the output capacitor. Because of different control mechanisms, the value of the load current where transition into CCM operation takes place is usually higher compared to the load level at which transition into hysteretic mode had occurred.
where: Ro -- is load resistance and Co -- is load capacitance. For this type of modulator, a Type 2 compensation circuit is usually sufficient. Figure 7 shows a Type 2 amplifier and its response along with the responses of the current mode modulator and the converter. The Type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole:
F Z 1 = ----------------------------- = 6kHz 2 R C 21
VOUT pin and Forced Continuous Conduction Mode (FCCM)
The controller has the flexibility to operate a converter in fixed-frequency constant conduction mode (CCM), or in hysteretic mode. Connecting the VOUT pin to GND will inhibit hysteretic mode; this is called forced constant conduction mode (FCCM). Connecting the VOUT pin to the converter output will allow transition between CCM mode and hysteretic mode. When the VOUT pin is connected to the converter output, a circuit is activated that smooths the transition from hysteretic mode to CCM mode. While in hysteretic mode, this circuit prepositions the PWM error amplifier output to a level close to that needed to provide the appropriate PWM duty cycle required for regulation. This is a much more desirable state for the PWM error amplifier at mode transition, as opposed to being in saturation which requires a period of time to slew to the required level. Such dual function of the VOUT pin enhances applicability of the controller and allows for lower pin count.
;
F
P
1 = ----------------------------- = 600kHz 2 R C 12
This region is also associated with phase `bump' or reduced phase shift. The amount of phase shift reduction depends on how wide the region of flat gain is and has a maximum value of 90o. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feed-forward of VIN to the oscillator ramp.
C2 CONVERTER R1 R2 C1
EA
Feedback Loop Compensation
To reduce the number of external components and remove the burden of determining compensation components from a system designer, both PWM controllers have internally compensated error amplifiers. To make internal compensation possible several design measures where taken. First, the ramp signal applied to the PWM comparator is proportional to the input voltage provided via the VIN pin. This keeps the modulator gain constant when the input voltage varies. Second, the load current proportional signal is derived from the voltage drop across the lower MOSFET during the PWM time interval and is added to the amplified error signal on the comparator input. This effectively creates an internal current control loop. The resistor connected to 9
GM=18dB MODULATOR FZ FPO FC
TYPE 2 EA
GEA=14dB FP
FIGURE 7. FEEDBACK LOOP COMPENSATION
ISL6225
The zero frequency, the amplifier high-frequency gain, and the modulator gain are chosen to satisfy most typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase `boost'. Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within 10kHz...50kHz range gives some additional phase `boost'. Some phase boost can also be achieved by connecting capacitor Cz in parallel with the upper resistor R1 of the divider that sets the output voltage value, as shown in Figure 4.
Protections
The converter output is monitored and protected against extreme overload, short circuit, Over-Voltage, and UnderVoltage conditions. A sustained overload on the output sets the PGOOD low and latches-off the whole chip. The controller operation can be restored by cycling the VCC voltage or an enable (EN) pin.
Over-Current Protection
Both PWM controllers use the lower MOSFET's on-resistance {RDS(ON)} to monitor the current for protection against shorted outputs. The sensed current from the ISEN pin is compared with a current set by a resistor connected from the OCSET pin to ground.
9.6V * ( R CS + 100 ) R OCSET = ----------------------------------------------------I OC * R DS ( ON )
Gate Control Logic
The gate control logic translates generated PWM signals into gate drive signals providing necessary amplification, level shift, and shoot-trough protection. Also, it bears some functions that help to optimize the IC performance over a wide range of the operational conditions. As MOSFET switching time can very dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring real gate waveforms of both the upper and the lower MOSFETs.
Where, IOC is a desired Over-Current protection threshold and RCS is the value of the current sense resistor connected to the ISEN pin. If the lower MOSFET current exceeds the Over-Current threshold, a pulse skipping circuit is activated. The upper MOSFET will not be turned on as long as the sensed current is higher then the threshold value. This limits the current supplied by the DC voltage source. This condition keeps on for eight clock cycles after the Over-Current comparator was tripped for the first time. If after these first eight clock cycles the current exceeds the Over-Current threshold again in a time interval of another eight clock cycles, the Over-Current protection latches and disables the chip. If the Over-Current condition goes away during the first eight clock cycles, normal operation is restored and the Over-Current circuit resets itself sixteen clock cycles after the Over-Current threshold was exceeded the first time, Figure 8.
Dual-Step Conversion
The ISL6225 dual channel controller can be used either in power systems with a single-stage power conversion when the battery power is converted into the desired output voltage in one step, or in the systems where some intermediate voltages are initially established. The choice of the approach may be dictated by the overall system design criteria or simply to be a matter of voltages available to the system designer, like in the case of PCI card applications. When the power input voltage is a regulated 5V or 3.3V system bus, the feed-forward ramp may become too shallow, which creates the possibility of duty-factor jitter especially in a noisy environment. The noise susceptibility when operating from low level regulated power sources can be improved by connecting the VIN pin to ground. The feedforward ramp generator will be internally reconnected from the VIN pin to the VCC pin and the ramp slew rate will be doubled. Application circuits for dual-step power conversion are presented in Figures 11 through 15.
1 IL 2
PGOOD
8 CLK SHUTDOWN
VOUT
3 Ch1 5.0V Ch3 1.0A Ch2 100mV M 10.0s
FIGURE 8. OVER-CURRENT PROTECTION WAVEFORMS
10
ISL6225
If load step is strong enough to pull output voltage lower than the Under-Voltage threshold, the chip shuts down immediately. Because of the nature of the used current sensing technique, and to accommodate wide range of the RDS(ON) variation, the value of the Over-Current threshold should represent overload current about 150%...180% of the nominal value. If more precise current protection is desired, a current sense resistor placed in series with the lower MOSFET source may be used. The ISL6225 dual channel PWM controller possesses several important means that allow re configuration for this particular application and provide all three voltages required in DDR memory compliant computer. To reconfigure the ISL6225 for a complete DDR solution, the DDR pin shall be permanently set high. The simplest way to do that is to connect it to the VCC rail. This activates some functions inside the chip that are specific to the DDR memory power needs. In DDR application presented in Figure 14 and 15, the first controller regulates the VDDQ rail to 2.5V. The output voltage is set by an external divider R3 and R5. The second controller regulates the VTT rail to VDDQ/2. The OCSET2 pin function is now different. The pin serves now as an input that brings VDDQ/2 voltage created by R4 and R6 divider inside the chip. That effectively provides a tracking function for the VTT voltage. The PG2 pin function is also different in DDR mode. This pin becomes the output of the buffer, which input is connected via the OCSET2 pin to the center point of the R/R divider from the VDDQ output. The buffer output voltage serves as 1.25V reference for the DDR memory chips. Current capability of this pin is about 10mA. For the VTT channel some control and protective functions can be significantly simplified as this output is derived from the VDDQ output. For example, the Over-Current and OverVoltage protections for the second controller are disabled when the DDR pin is set high. The hysteretic mode of operation is also disabled on the VTT channel to allow sinking capability to be independent from the load level. As the VTT channel tracks the VDDQ/2 voltage, the soft-start function is not required and the SOFT2 pin may be left open.
Over-Voltage Protection
Should the output voltage increase over 115% of the normal value due to the upper MOSFET failure, or other reasons, the Over-Voltage protection comparator will force the synchronous rectifier gate driver high. This action actively pulls down the output voltage and eventually attempts to blow the battery fuse. As soon as the output voltage drops below the threshold, the OVP comparator is disengaged. This OVP scheme provides a `soft' crowbar function which helps to tackle severe load transients and does not invert the output voltage when activated -- a common problem for OVP schemes with a latch.
Over-Temperature Protection
The chip incorporates an over-temperature protection circuit that shuts the chip down when the die temperature of 150oC is reached. Normal operation restores at die temperatures below 125oC through the full soft-start cycle.
DDR Application
Double Data Rate (DDR) memory chips are expected to take the place of traditional memory in many newly designed computers, including high-end notebooks, due to increased throughput. A novel feature associated with this type of memory is new referencing and data bus termination techniques. These techniques employ a reference voltage, VREF, that tracks the center point of VDDQ and VSS voltages and an additional VTT power source to which all terminating resistors are connected. Despite the additional power source, the overall memory power consumption is reduced compared to traditional termination. The added power source has a cluster of requirements that should be observed and considered. Due to reduced differential thresholds of DDR memory, the termination power supply voltage, VTT, shall closely track VDDQ/2 voltage. Another very important feature for the termination power supply is a capability to equally operate in sourcing and sinking modes. The VTT supply shall regulate the output voltage with the same degree of precision when current is floating from the supply to the load and when the current is diverted back from the load into the power supply. The last mode of operation usually conflicts with the way most PWM controllers operate. 11
Channel Synchronization in DDR Applications
Presence of two PWM controllers on the same die require channel synchronization to reduce inter channel interference that may cause the duty factor jitter and increased output ripple. The PWM controller is mostly susceptible to noise when an error signal on the input of the PWM comparator approaches the decision making point. False triggering can occur causing jitter and affecting the output regulation. Out-of-phase operation is a common approach to synchronize dual channel converters as it reduces an input current ripple and provides a minimum interference for channels that control different voltage levels. When used in DDR application with cascaded converters (VTT generated from VDDQ), the turn-on of the upper MOSFET in the VDDQ channel happens to be just before the decision making point in the VTT channel that is running with a duty-factor close to 50%, as in Figure 10.
ISL6225
This makes out-of-phase channel synchronization undesirable when one of the channels is running on a dutyfactor of 50%. Inversely, the in-phase channel arrangement does not have this drawback. Points of decision are far from noisy moments of time in both sourcing and sinking modes of operation for VIN=7.5V to 24V as it is shown in Figure 9. In the case when power for VDDQ is taken from the +5V system rail, as Figure 10 shows, both in-phase and out-ofphase approaches are susceptible to noise in the sourcing mode.
300kHz CLOCK
Several ways of synchronization are implemented into the chip. When the DDR pin is connected to GND, the channels operate 180o out-of-phase. In the DDR mode when the DDR pin is connected to VCC, the channels operate either inphase when the VIN pin is connected to the input voltage source, or with 90o phase shift if the VIN pin is connected to GND.
ISL6225 DC-DC Converter Application Circuits
Figures 11 and 12 show application circuits of a dual channel DC/DC converter for a notebook PC. The power supply in Figure 11 provides +2.5V and +1.8V for memory and graphic interface chipset from +5.0V to +24V battery voltage. Figure 12 shows the power supply that provides +2.5V and +1.8V for memory and graphic interface chipset from +5.0V system rail. Figure 13 shows an application circuit for a single-output split input power supply with current sharing for advanced graphic card applications.
VDDQ
SOURCING
VTT
OUT-OF-PHASE
SINKING SOURCING VTT IN-PHASE
SINKING
FIGURE 9. CHANNEL INTERFERENCE VIN=7.5V...24V
Noise immunity can be improved by operating the VTT converter with a 90o phase shift. As the time diagrams in Figure 10 show, the points of concern are always about a quarter of the period away from the noise emitting transitions.
300kHz CLOCK
Figure 14 and 15 show application circuits of a complete power solution for DDR memory that becomes a preferred choice in modern computers. The power supply shown in Figure 14 generates +2.5V VDDQ voltage from +5.0V to +24V battery voltage. The +1.25V VTT termination voltage tracks VDDQ/2 and is derived from +2.5V VDDQ. To complete the DDR memory power requirements, the +1.25V reference voltage is also provided. The PG2 pin serves as an output for the reference voltage in this mode. Figure 15 depicts the DDR solution in the case where the 5V system rail is used as a primary voltage source. For detailed information on the circuit, including a Bill-ofMaterials and circuit board description, see Application Note AN9995. Also see Intersil's web site (http://www.intersil.com) for the latest information.
VDDQ
SOURCING VTT SINKING SOURCING VTT SINKING IN-PHASE OUT-OF-PHASE
SOURCING 90o PHASE SHIFT
VTT
SINKING
FIGURE 10. CHANNEL INTERFERENCE VIN=5V
12
ISL6225
VIN +5.0V to +24V VCC CR1 BAT54 WT1 C1 1.0F + C2 10F C6 0.15F VIN BOOT1 CR2 BAT54 WT1 GND 1 14 6 C7 0.15F VCC BOOT2 + C10 10F +5V
+
DDR 13 28 23
C5 10F
Q1 +2.50V 3.0A L1 10H 1/2 FDS6912A R1 2.00K R3 17.8K C11 15nF + C8 330F Q2
UGATE1 PHASE1
5 4
24 25
UGATE2 PHASE2
Q3 L2 10H 1/2 FDS6912A R2 2.00K +1.80V 2.0A
ISEN1
7
22
ISEN2
LGATE1 PGND1
2 3
ISL6225
27 26
LGATE2 PGND2
Q4
C9 + 330F
R4 10K C12 15nF
2/2 FDS6912A
2/2 FDS6912A
VOUT1 VSEN1 VPULLUP OCSET1 SOFT1 EN1 R5 10K R9 100K R7 100K C3 10nF
9 10 11 12 8 15 PG1 16
20 19 18 17 21
VOUT2 VSEN2 OCSET2 SOFT2 EN2 C4 10nF R8 100K R6 10K
PG2/REF
POWER GOOD CH1 ENABLE POWER GOOD CH2
FIGURE 11. DUAL OUTPUT APPLICATION CIRCUIT FOR ONE-STEP CONVERSION
13
ISL6225
VCC CR1 BAT54 WT1 C1 1.0F + C2 10F C6 0.15F VIN BOOT1 CR2 BAT54 WT1 GND 1 14 6 C7 0.15F VCC BOOT2 +5V
+
DDR 13 28 23
C5 10F
Q1 +2.50V 3.0A L1 4.7H 1/2 FDS6912A R1 2.00K R3 17.8K C11 15nF + C8 330F Q2
UGATE1 PHASE1
5 4
24 25
UGATE2 PHASE2
Q3 L2 4.7H 1/2 FDS6912A R2 2.00K +1.80V 2.0A
ISEN1
7 ISL6225
22
ISEN2
LGATE1 PGND1
2 3
27 26
LGATE2 PGND2
Q4
C9 + 330F
R4 10K C12 15nF
2/2 FDS6912A
2/2 FDS6912A
VOUT1 VSEN1 VPULLUP OCSET1 SOFT1 EN1 R5 10K R9 100K R7 100K C3 10nF
9 10 11 12 8 15 PG1 16
20 19 18 17 21
VOUT2 VSEN2 OCSET2 SOFT2 EN2 C4 10nF R8 100K R6 10K
PG2/REF
POWER GOOD CH1 ENABLE POWER GOOD CH2
FIGURE 12. DUAL OUTPUT APPLICATION CIRCUIT FOR TWO-STEP CONVERSION
14
ISL6225
VIN +12V VCC +5V
CR1 BAT54 WT1 C1 1.0F + C2 10F C6 0.15F VIN BOOT1
CR2 BAT54 WT1 GND 1 14 6 C7 0.15F VCC BOOT2
+
DDR 13 28 23
C5 10F
Q1 L1 10H 1/2 FDS6912A R1 2.00K R3 6.65K C12 15nF + C8 330F Q2
UGATE1 PHASE1
5 4
24 25
UGATE2 PHASE2
Q3 L2 4.7H 1/2 FDS6912A
ISEN1
7 ISL6225
22
ISEN2
R2 2.00K
LGATE1 PGND1
2 3
27 26
LGATE2 PGND2
Q4
C9 + 330F
R4 6.65K C13 15nF
2/2 FDS6912A
2/2 FDS6912A
VOUT1 VSEN1 VPULLUP OCSET1 SOFT1 EN1 R5 10K R9 100K R7 100K C3 10nF
9 10 11 12 8 15 PG1 16
20 19 18 17 21
VOUT2 VSEN2 OCSET2 SOFT2 EN2 C4 10nF R8 100K R6 10K
PG2/REF
POWER GOOD CH1 ENABLE POWER GOOD CH2
R10 0.01
R11 0.01
C10 + 330F +1.50V 8.0A
+ C11 330F
FIGURE 13. SINGLE-OUTPUT SPLIT INPUT POWER SUPPLY
15
ISL6225
VIN +5.0V to +24V VCC CR1 BAT54 WT1 C1 1.0F + C2 10F C6 0.15F VIN BOOT1 CR2 BAT54 WT1 GND 1 14 6 C7 0.15F VCC BOOT2 + C11 10F +5V
+
DDR 13 28 23
C5 10F
Q1 +2.50V 3.0A VDDQ L1 4.6H ~ 6.0A
UGATE1 PHASE1
5 4
24 25
UGATE2 PHASE2
Q3 L2 1.5H 1/2 FDS6912A R2 1.00K +1.25V 3.0A VTT
1/2 FDS6912A R1 2.49K ISEN1 7 22 ISEN2
R3 17.8K C12 15nF
+ C8 330F
Q2
LGATE1 PGND1
2 3
ISL6225
27 26
LGATE2 PGND2
Q4
C9 + 330F
R4 10K
2/2 FDS6912A
2/2 FDS6912A
VOUT1 VSEN1 VPULLUP OCSET1 SOFT1 EN1 R5 10K R9 100K R7 100K C3 10nF
9 10 11 12 8 15 PG1 16
20 19 18 17 21
VOUT2 VSEN2 OCSET2 SOFT2 EN2 C10 10nF R6 10K
PG2/REF
POWER GOOD CH1 ENABLE VREF C4 4.7F
FIGURE 14. APPLICATION CIRCUIT FOR COMPLETE DDR MEMORY POWER SOLUTION WITH ONE-STEP CONVERSION
16
ISL6225
VCC CR1 BAT54 WT1 C1 1.0F + C2 10F C6 0.15F VIN BOOT1 CR2 BAT54 WT1 GND 1 14 6 C7 0.15F VCC BOOT2 + C10 10F +5V
+
DDR 13 28 23
C11 10F
Q1 +2.50V 3.0A VDDQ L1 4.6H ~ 6.0A 1/2 FDS6912A R1 2.49K R3 17.8K C12 15nF + C8 330F Q2
UGATE1 PHASE1
5 4
24 25
UGATE2 PHASE2
Q3 L2 1.5H 1/2 FDS6912A R2 1.00K +1.25V 3.0A VTT
ISEN1
7
22
ISEN2
LGATE1 PGND1
2 3
ISL6225
27 26
LGATE2 PGND2
Q4
C9 + 330F
R4 10K
2/2 FDS6912A
2/2 FDS6912A
VOUT1 VSEN1 VPULLUP OCSET1 SOFT1 EN1 R5 10K R9 100K R7 100K C3 10nF
9 10 11 12 8 15 PG1 16
20 19 18 17 21
VOUT2 VSEN2 OCSET2 SOFT2 EN2 C5 10nF R6 10K
PG2/REF
POWER GOOD CH1 ENABLE VREF C4 4.7F
FIGURE 15. APPLICATION CIRCUIT FOR COMPLETE DDR MEMORY POWER SOLUTION WITH TWO-STEP CONVERSION
17
ISL6225 Shrink Small Outline Plastic Packages (SSOP)
N INDEX AREA E -B1 2 3 L SEATING PLANE -AD -CA 0.25 0.010 h x 45o GAUGE PLANE H 0.25(0.010) M BM
M28.15
LEAD SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B C D E e MIN 0.053 0.004 0.008 0.007 0.386 0.150 MAX 0.069 0.010 0.061 0.012 0.010 0.394 0.157 MILLIMETERS MIN 1.35 0.10 0.20 0.18 9.81 3.81 MAX 1.75 0.25 1.54 0.30 0.25 10.00 3.98 NOTES 9 3 4 5 6 7 8
o
0.025 BSC 0.228 0.0099 0.016 28 0
o
0.635 BSC 5.80 0.26 0.41 28
o
A1 0.10(0.004) A2 C
H h L N
0.244 0.0196 0.050
o
6.19 0.49 1.27
e
B 0.17(0.007) M C A M BS
NOTES: 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 4. Dimensioning and tolerancing per ANSI Y14.5M-1982. 5. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 6. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 7. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 8. "L" is the length of terminal for soldering to a substrate. 9. "N" is the number of terminal positions. 10. Terminal numbers are shown for reference only. 11. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 12. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
8
0
Rev. 0 2/95
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18

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